Atmel's CAPs ("customizable Atmel processor") integrates the ARM9 core with a metal-programmable function block where users can implement additional cores, DSPs (digital signal processors), or custom peripherals. The
AT91CAP9, released in June 2007, is the first CAP processor, clocked at 200 MHz and offering 250K or 500K metal programmable gates.
According to Atmel, the programmable block can be used to add an additional ARM9 or AVR32 processor core, DSP core, or custom peripherals not available on off-the-shelf SoCs (system-on-chip processors). A 6-layer AHB bus and distributed DMA architecture is said to provide lots of on-chip bandwidth, suitable for deeply embedded networked applications.
Atmel AT91CAP9S chip architecture
(Click to enlarge)AT91CAP9S peripheral support includes a full-speed USB host port, high-speed USB device port, 10/100 Ethernet MAC, image sensor interface, 2.0A and 2.0B CAN controller, LCD controller, MCI, SSC, PWM, LCD and AC97 controllers, SPI master and slave, two USARTs, three 16-bit timer counters, an 8-channel, 10-bit analog to digital converter, and various supervisory functions, Atmel says. Optional hardware AES/TDES encryption/decryption engines are also available.
It's said Adeneo was integrally involved in the design and production of Atmel's AT91CAP9A-STK starter kit (seen below). The kit is built on a single PCB and includes the following features, according to Atmel:
- Processor -- AT91CAP9S ARM926EJ-S-based system-on-chip (SoC), clocked at 200MHz
- Memory -- 64MB of SDRAM, and 512MB of NAND flash, plus up to 8MB of "DataFlash"
- Networking -- 10/100 Ethernet interface
- Other I/O:
- USB host and device ports
- Output for QVGA (320 x 240) touchscreen display
- SD card interface
- 4 analog inputs
- headphone outputAtmel says the kit also includes Altera's Stratix2 EP2S15F484 FPGA and its associated EPCS16 serial configuration memory. The FPGA provides 15600 four-input Lookup Table (LUT) equivalents, corresponding to approximately 124800 gates in the CAP MP Block.
ATMEL's CAP starter kit
The kit offers 64 general-purpose I/O connections from the AT91CAP9S, and 2 banks of 64 I/Os from the FPGA, for application-specific external interfaces, adds Atmel. System debug is said to be facilitated by an ICE-JTAG interface for CAP9 JTAG programming, and a USB-Blaster-JTAG interface for Stratix2 JTAG programming.
Finally, the BSP included with the starter kit consists of a fully supported Windows CE 6.0 kernel ported onto the AT91CAP9 architecture, with drivers for all the CAP peripherals and external interfaces. Drivers for the additional functional modules implemented in the CAP Metal Programmable (MP) Block can be seamlessly integrated, according to Adeneo.
Michel Le Lan, Atmels Marketing Director for ASIC products, said, "Adeneos Windows Embedded CE BSP for the CAP Development and Starter Kits is a major step towards our goal of simplifying application development for CAP customers. A fully featured operating system like ... CE enables CAP applications to fully exploit the potential of CAPs multiple peripherals and interfaces with a minimum programming overhead."
Availability
A free binary evaluation version of the AT91CAP9 BSP is available for download from Adeneos Web site, here. A full source code set is also available for a free 20-day evaluation period under nondisclosure agreement (NDA).
The CAP starter kit, which appears to be available now, includes not only the BSP, but a "KickStart" version of IAR Embedded Workbench for ARM, and instructions for downloading Alteras free Quartus 2 Web Edition tools for FPGA programming, according to Atmel.
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