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        MIPS processors gain DSP instructions

        Staff | Date: Oct 5, 2004 | Comments: 1



        A new DSP (digital signal processing) extension will appear in future MIPS processor cores, and is available now for licensed use in SoC (system-on-chip) designs. MIPS Technology's DSP ASE (application-specific extension) aims to help device designers eliminate discreet DSP coprocessors, shaving costs in high-volume consumer electronic devices such as DVD recorders, digital cameras, residential...


        gateways, and VoIP (voice over IP) phones.

        According to MIPS, the new DSP extension comprises a "set of new instructions and states in the integer pipeline" of MIPS cores. It is said to require under six percent of additional silicon area to implement in a 24K-class core, while improving signal processing performance a claimed 300 percent.

        Additionally, MIPS says the new DSP extension offers programmability that allows adaptation to changing market needs, extending the life of an SoC design.

        Features of the MIPS DSP ASE include:
        • 8-, 16- and 32-bit SIMD instructions
        • Saturating and fractional math
        • Popular DSP operations, such as MAC, dot-product, absolute, and complex-multiply
        • Key features such as variable bit insert/extract and virtual circular buffers
        Tools, library and operating system support:
        • MIPS Software Toolkit support: tuned compiler (C front-end), assembler, debugger, instruction-set simulator, and performance analysis tools
        • The MIPS DSP Library: a set of key DSP functions, including DCT, FFT, filters, and other popular functions
        "With the MIPS DSP ASE and DSP Library, SOC designers can leverage many popular DSP algorithms and support tools needed to efficiently process media tasks," said Will Strauss, CEO of Forward Concepts, an Arizona-based market research firm.

        Availability

        The DSP ASE is available for licensing by MIPS32 and MIPS64 ISA customers. Additionally, this technology will appear in future 32- and 64-bit cores developed by MIPS Technologies.



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