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MIPS Technologies announces availability of "fastest licensable core"
Feb. 13, 2002

Mountain View, CA -- (press release excerpt) -- The embedded processor industry's highest performance licensable processor core is now available to customers for design starts, MIPS Technologies, Inc. announced today. The 64-bit, 600-MHz MIPS64 20Kc hard core at a 0.13-micron fabrication process achieves performance of 1370 Dhrystone 2.1 MIPS (with inlining). The 20Kc microarchitecture is designed to scale to 1 GHz in a 0.10-micron process. The core already is available at 400 MHz in TSMC's 0.18G-micron process.

The superscalar 20Kc core gives semiconductor suppliers and OEMs the highest system performance available for cost- and power-sensitive applications such as multimedia home gateways, automotive telematics, networking, office automation and game consoles. The core's processing power allows systems designers to reduce end product cost by integrating in software many features traditionally handled by dedicated hardware blocks. The 20Kc core also meets and exceeds emerging standards and feature requirements in applications such as set-top boxes, residential gateways and high-end printers.

Features of the 20Kc core include:
  • Dual-issue, superscalar, 7-stage pipeline.
  • Integer and floating-point performance unprecedented for a licensable core. Its 64-bit dual-issue integer capability and double-precision IEEE-754 floating-point unit (FPU) allow the core to achieve a performance of 1370 Dhrystone 2.1 MIPS (with inlining) and peak 2.4 Gflops at 600 MHz.
  • SIMD (single-instruction, multiple data) instructions in the FPU that greatly accelerate the processing of large data streams, eliminating the need for a separate DSP and thereby lowering the cost of the end product.
  • Power dissipation of 1.5 watts for the full core at 600 MHz, at 1.0 volt.
  • Core size is a small 8 mm2. With two 32-Kbyte caches, memory management unit and floating-point unit, core size is 20 mm2.
The 20Kc core also features a new, high-bandwidth interface, the MGB Link, to help eliminate performance bottlenecks. This gives designers an industry-leading, peak 3.6-Gbytes per second interface in an SOC environment, a significant benefit when moving very large data streams and graphics files. The MGB Link is designed to scale to meet future throughput needs by allowing for wider bus widths and higher clock speeds.



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