| Configurable 65nm ARM9 chip costs $6, runs Windows CE |
May 27, 2008
 STMicroelectronics (STM) has announced an ARM9-based SoC (system-on-chip) that runs Windows CE and targets printers, scanners, and digital picture frames. The "SPEAr Basic" has an ARM926EJ-S core, a 300Kgate customizable logic array, 10/100 Ethernet, USB, serial, IrDA, and a 72KB internal memory pool, the company says.
STM says this new SoC is the first in its SPEAr (structured processor enhanced architecture) family of products to use 65nm processor technology, giving it "increased density, performance and power-reduction." The device includes an ARM926EJ-S processor core, clocked at 333MHz, with two 16k memory caches. Added to this is a customizable logic array that offers 72KB of configurable internal memory, 102 I/O lines, and up to 300,000 ASIC-equivalent gates.
The SPEAr Basic's customizable logic block is touted as allowing high performance, quick development, and a "full custom design approach." Via the separately available SPEAr Plus600 development kit and its external FPGA, which mirrors the SoC's internal configurable logic block, designers can proceed with software and hardware development without waiting for final validation. Once the customer's SoC passes the functional qualification, full production can typically ramp up in eight to ten weeks' time from the final RTL availability, the company says.
A block diagram of the SPEAr Basic
(Click to enlarge)
The SPEAr Basic comes in a 15 x 15 x 0.8mm LFBGA (low profile fine pitch ball grid array) package, and has an operating temperature from -40 to 85 deg. C. Its core features, as shown on the block diagram above, include the following:- Multilayer AMBA 2.0 compliant bus
- 32Kb boot ROM
- 1 x USB 2.0 device with integrated PHY
- 2x USB 2.0 host with integrated PHY
- High-performance 8-channel DMA
- Ethernet 10/100 MAC with MII interface to external PHY
- External DRAM memory interface:
- 8/16 bits (LP-DDR @ 166 MHz)
- 8/16 bits (DDR2 @ 333 MHz)
- Flash interface -- SPI serial (up to 50Mbit/s)
- SPI master/slave up to 50Mbit/s
- I2C master/slave mode –- high, fast and slow speed
- UART up to 460.8Kbps
- IrDA (FIR/MIR/SIR) from 9.6Kbps to 4Mbps
- 10-bit ADC
- JPEG codec accelerator
- Real-time clock
- Watchdog timer
- System controller
- JTAG and ETM (embedded trace macrocell for debug operations)
- C3 crypto accelerator (DES/3DES/AES/SHA1)
Additional functionality is implemented as default customizations of the 300Kgate logic block. As listed by STM, it includes:- LCD controller, supporting TFT/STN displays and resolution up to 1024 x 768 pixels
- 9 x 9 keyboard controller
- Flexible static memory controller, supporting NAND/NOR parallel flash or SRAM
- SDIO/MMC card interface
- ITU-601 camera interface supporting external and embedded sync
- TDM master/slave:
- 1024 TDM channels with switching capability
- Up to 16 channels bufferized (30ms) for VoIP
- I2S compliant
- Glueless management of up to 8 SLICs/codecs
- Up to 8 I2C/SPI extensions
- 1-bit DAC (order 2 noise shaper)
- Up to 18 GPIOs, 8 with interrupt capability
The SPEAr Basic runs Windows CE, Linux, VXWorks, or ThreadX operating systems. It is sampling now and will be available in quantity during the third quarter. The price is $6, in quantities above 20K.
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