| Intel prepping Pentium M-based SoC? |
Feb. 06, 2007
Intel reportedly will ship a super-high-integration IA32 SoC (system-on-chip) in late 2007, with a development board available in Q2. The "Tolapai" design integrates a Pentium M core, northbridge, and southbridge into a single 37.5mm-square chip clocked from 600MHz to 1.2GHz, according to presentation slides posted at Chinese technology website HKEPC.
Contrary to reports elsewhere on the Web, the Tolapai processor does not appear to be aimed at the small form-factor PC market served by x86-compatible chipsets with integrated graphics, such as Via's C7 and AMD's Geode LX800. Instead, Tolapai will ship with various peripheral mixes aimed at appealing to more traditional embedded markets, including industrial control and automotive, and also telecommunications -- including both control plane (management) and signal processing (line-card) applications.
The HKEPC story suggests that Tolapai will run standard 32-bit Intel Architecture (IA32) operating systems, including Windows XP Embedded, without modification to applications or drivers. Other officially supported OSes appear to include FreeBSD and Linux, specifically Red Hat.
The Tolapai chip is based on a Pentium M core with 256KB of L2 cache. It also has an integrated memory controller hub (IMCH, or northbridge), and an integrated I/O controller hub (IICH, or southbridge). It does not appear to have an integrated graphics processor, however.
Clocked at 600MHz, 1.0GHz, or 1.2GHz, Tolapai will have a thermal design power (TDP) between 13 and 25 Watts. It will supposedly support up to 2GB of DDR2 clocked from 400MHz to 800MHz, optionally with ECC (error checking and correction), in single- or dual-channel configurations.
Tolapai's on-chip peripheral interface mix appears to include the following:- 3 x gigabit Ethernet (RGMII or RMII)
- 1 x MDIO
- 2 x CAN (controller area network), possibly optional
- 1 x SSP (sync serial port)
- 2 x UART, 33 GPIO
- 2 x SMBus/I2C, LPC 1.1
- 2 x USB 1.1/2.0, 2 x SATA 1.0/2.0
- PCI Express (1x8, 2x4, 2x1)
Additionally, the Tolapai design will be available with on-chip acceleration for cryptographic functions that include AES, 3DES, RC4, MD5, SHA-1, SHA-224-256-384-512, HMAC, ESA and DSA, with claimed throughputs up to 1.6Gbps.
A reference board based on Tolapai will integrate a five-port switch on a four-lane PCIe port, three gigabit Ethernet interfaces, a pair of DDR2 800 DIMM slots, dual USB ports, mezzanine connectors for expansion bus interfaces (up to three mezzanine connectors for TDM, for instance), and optional hard drives.
The HKEPC story can be found here.
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